URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 366

Rev	Log message	Author	Age	Path
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7880d 02h	/ethmac/trunk/rtl/verilog/ethmac.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7880d 03h	/ethmac/trunk/rtl/verilog/ethmac.v
248	wb_rst_i is used for MIIM reset.	mohor	7881d 03h	/ethmac/trunk/rtl/verilog/ethmac.v
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7885d 02h	/ethmac/trunk/rtl/verilog/ethmac.v
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7885d 22h	/ethmac/trunk/rtl/verilog/ethmac.v
227	Changed BIST scan signals.	tadejm	7912d 03h	/ethmac/trunk/rtl/verilog/ethmac.v
218	Typo error fixed. (When using Bist)	mohor	7919d 07h	/ethmac/trunk/rtl/verilog/ethmac.v
214	Signals for WISHBONE B3 compliant interface added.	mohor	7920d 03h	/ethmac/trunk/rtl/verilog/ethmac.v
210	BIST added.	mohor	7920d 04h	/ethmac/trunk/rtl/verilog/ethmac.v
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7940d 03h	/ethmac/trunk/rtl/verilog/ethmac.v