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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 131

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Rev Log message Author Age Path
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8096d 05h /ethmac/trunk/rtl/verilog
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8096d 06h /ethmac/trunk/rtl/verilog
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8096d 06h /ethmac/trunk/rtl/verilog
97 Small typo fixed. lampret 8120d 03h /ethmac/trunk/rtl/verilog
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8124d 03h /ethmac/trunk/rtl/verilog
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8124d 06h /ethmac/trunk/rtl/verilog
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8124d 06h /ethmac/trunk/rtl/verilog
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8129d 04h /ethmac/trunk/rtl/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8130d 07h /ethmac/trunk/rtl/verilog
91 Comments in Slovene language removed. mohor 8130d 07h /ethmac/trunk/rtl/verilog

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