URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 160

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7988d 03h	/ethmac/trunk/rtl/verilog
126	InvalidSymbol generation changed.	mohor	7988d 04h	/ethmac/trunk/rtl/verilog
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7988d 04h	/ethmac/trunk/rtl/verilog
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7990d 05h	/ethmac/trunk/rtl/verilog
120	Unused files removed.	mohor	7990d 06h	/ethmac/trunk/rtl/verilog
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7990d 06h	/ethmac/trunk/rtl/verilog
118	ShiftEnded synchronization changed.	mohor	7993d 21h	/ethmac/trunk/rtl/verilog
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7995d 06h	/ethmac/trunk/rtl/verilog
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7996d 03h	/ethmac/trunk/rtl/verilog
113	RxPointer bug fixed.	mohor	8002d 19h	/ethmac/trunk/rtl/verilog