URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 63

Rev	Log message	Author	Age	Path
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8156d 04h	/ethmac/trunk/rtl/verilog
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8165d 06h	/ethmac/trunk/rtl/verilog
37	Link in the header changed.	mohor	8165d 06h	/ethmac/trunk/rtl/verilog
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8214d 02h	/ethmac/trunk/rtl/verilog
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8214d 06h	/ethmac/trunk/rtl/verilog
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8214d 07h	/ethmac/trunk/rtl/verilog
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8236d 03h	/ethmac/trunk/rtl/verilog
24	Log file added.	mohor	8261d 05h	/ethmac/trunk/rtl/verilog
23	Number of addresses (wb_adr_i) minimized.	mohor	8261d 06h	/ethmac/trunk/rtl/verilog
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8261d 08h	/ethmac/trunk/rtl/verilog