URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 59

Rev	Log message	Author	Age	Path
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7889d 17h	/i2c/trunk/rtl
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8027d 04h	/i2c/trunk/rtl
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8244d 00h	/i2c/trunk/rtl
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8248d 23h	/i2c/trunk/rtl
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8248d 23h	/i2c/trunk/rtl
13	Fixed some synthesis warnings.	rherveille	8260d 03h	/i2c/trunk/rtl
11	Changed RST_LVL define to parameter.	rherveille	8269d 02h	/i2c/trunk/rtl
10	Created new directory structure. Added Verilog version.	rherveille	8290d 23h	/i2c/trunk/rtl