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[/] [ion/] [trunk/] [vhdl/] - Rev 107

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Rev Log message Author Age Path
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses
ja_rd 4906d 16h /ion/trunk/vhdl
60 Forgot to upload new TB package!!
Without this, simulations don't work...
ja_rd 4906d 16h /ion/trunk/vhdl
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 4908d 06h /ion/trunk/vhdl
58 Cleaned up cache stub code ja_rd 4908d 16h /ion/trunk/vhdl
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit
ja_rd 4908d 18h /ion/trunk/vhdl
48 Temporary fix to memory decoding constants ja_rd 4908d 22h /ion/trunk/vhdl
47 Pre-generated simulation test benches updated ja_rd 4908d 22h /ion/trunk/vhdl
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache
ja_rd 4908d 22h /ion/trunk/vhdl
43 added comments to dummy 'cache' stub ja_rd 4911d 06h /ion/trunk/vhdl
42 Added cache stub module, plus related test bench ja_rd 4913d 00h /ion/trunk/vhdl

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