URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 175

Rev	Log message	Author	Age	Path
126	added SDRAM verilog simulation model	ja_rd	4794d 23h	/ion/trunk/vhdl
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	4840d 23h	/ion/trunk/vhdl
120	Updated main package with lots of wait states for all areas	ja_rd	4850d 01h	/ion/trunk/vhdl
119	Updated pre-generated simulation and synthesis demos	ja_rd	4850d 01h	/ion/trunk/vhdl
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4850d 02h	/ion/trunk/vhdl
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	4850d 04h	/ion/trunk/vhdl
114	ADDED: 1st version of real cache	ja_rd	4850d 05h	/ion/trunk/vhdl
112	Updated simulation package for compatibility to new cache	ja_rd	4850d 06h	/ion/trunk/vhdl
103	ADDED cache control inputs (unused) to dummy cache	ja_rd	4858d 21h	/ion/trunk/vhdl
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4858d 21h	/ion/trunk/vhdl