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[/] [ion/] [trunk/] [vhdl] - Rev 152

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Rev Log message Author Age Path
112 Updated simulation package for compatibility to new cache ja_rd 4850d 12h /ion/trunk/vhdl
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4859d 03h /ion/trunk/vhdl
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4859d 03h /ion/trunk/vhdl
98 CPU rd and wr data address buses unified ja_rd 4883d 12h /ion/trunk/vhdl
96 CPU rd and wr data address buses unified ja_rd 4883d 12h /ion/trunk/vhdl
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4894d 09h /ion/trunk/vhdl
94 Pregenerated demo 'hello' files updated ja_rd 4894d 09h /ion/trunk/vhdl
85 BUG FIX: log2 function was wrong ja_rd 4894d 09h /ion/trunk/vhdl
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script
ja_rd 4894d 09h /ion/trunk/vhdl
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong
ja_rd 4894d 09h /ion/trunk/vhdl

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