URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk] - Rev 50

Rev	Log message	Author	Age	Path
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4900d 18h	/ion/trunk
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4900d 19h	/ion/trunk
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4900d 19h	/ion/trunk
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4900d 20h	/ion/trunk
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4901d 00h	/ion/trunk
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4901d 00h	/ion/trunk
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4901d 00h	/ion/trunk
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4901d 00h	/ion/trunk
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4901d 21h	/ion/trunk
21	Converted multiplier module reset to synchronous	ja_rd	4902d 08h	/ion/trunk