URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion] - Rev 51

Rev	Log message	Author	Age	Path
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4917d 09h	/ion
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4919d 05h	/ion
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4919d 06h	/ion
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4919d 06h	/ion
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4919d 08h	/ion
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4919d 11h	/ion
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4919d 11h	/ion
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4919d 11h	/ion
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4919d 11h	/ion
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4920d 09h	/ion