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Rev Log message Author Age Path
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 4938d 04h /ion
58 Cleaned up cache stub code ja_rd 4938d 14h /ion
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit
ja_rd 4938d 16h /ion
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly
ja_rd 4938d 16h /ion
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)
ja_rd 4938d 17h /ion
54 Doc updated
Cache section (2.7) is still missing
ja_rd 4938d 19h /ion
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.
ja_rd 4938d 20h /ion
52 Sim scripts adapted to recent changes ja_rd 4938d 20h /ion
51 Adapted simulation and synth templates for cache module ja_rd 4938d 20h /ion
50 New code sample: memtest
Tests external RAM
ja_rd 4938d 20h /ion

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