URL https://opencores.org/ocsvn/mlite/mlite/trunk

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[/] [mlite/] [trunk/] - Rev 145

Rev	Log message	Author	Age	Path
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7439d 13h	/mlite/trunk
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7503d 13h	/mlite/trunk
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7515d 02h	/mlite/trunk
120	Make generics "GENERIC"	rhoads	7515d 02h	/mlite/trunk
119	Opcodes from count.c	rhoads	7553d 13h	/mlite/trunk
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7553d 13h	/mlite/trunk
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7553d 13h	/mlite/trunk
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7553d 13h	/mlite/trunk
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7553d 13h	/mlite/trunk
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7553d 13h	/mlite/trunk