URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 103

Rev	Log message	Author	Age	Path
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4339d 17h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4343d 10h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
43	made the core parameters generics	JonasDC	4343d 10h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4349d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
41	removed deprecated files from version control	JonasDC	4349d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
40	adjusted core instantiation to new core module name	JonasDC	4357d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4358d 09h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4358d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4362d 12h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4363d 08h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl