URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 44

Rev	Log message	Author	Age	Path
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4254d 15h	/mod_sim_exp/tags/Release_1.4
23	added descriptive comments	JonasDC	4254d 16h	/mod_sim_exp/tags/Release_1.4
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4257d 09h	/mod_sim_exp/tags/Release_1.4
21	changed x_i signal to xi	JonasDC	4258d 17h	/mod_sim_exp/tags/Release_1.4
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4258d 17h	/mod_sim_exp/tags/Release_1.4
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4263d 12h	/mod_sim_exp/tags/Release_1.4
18	updated stages with comments and renamed some signals for consistency	JonasDC	4264d 12h	/mod_sim_exp/tags/Release_1.4
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4264d 17h	/mod_sim_exp/tags/Release_1.4
16	package with modified generic parameter for register_n	JonasDC	4265d 06h	/mod_sim_exp/tags/Release_1.4
15	changed generic for register width from n to width for consistency	JonasDC	4265d 06h	/mod_sim_exp/tags/Release_1.4