URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 74

Rev	Log message	Author	Age	Path
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4111d 02h	/mod_sim_exp/trunk
47	added documentation for the IP core.	JonasDC	4191d 02h	/mod_sim_exp/trunk
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4191d 02h	/mod_sim_exp/trunk
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4191d 02h	/mod_sim_exp/trunk
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4194d 19h	/mod_sim_exp/trunk
43	made the core parameters generics	JonasDC	4194d 19h	/mod_sim_exp/trunk
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4201d 03h	/mod_sim_exp/trunk
41	removed deprecated files from version control	JonasDC	4201d 03h	/mod_sim_exp/trunk
40	adjusted core instantiation to new core module name	JonasDC	4209d 07h	/mod_sim_exp/trunk
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4209d 18h	/mod_sim_exp/trunk