URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 77

Rev	Log message	Author	Age	Path
53	correctly inferred ram for altera dual port ram	JonasDC	4121d 02h	/mod_sim_exp/trunk
52	correct inferring of blockram, no additional resources.	JonasDC	4121d 03h	/mod_sim_exp/trunk
51	true dual port ram for xilinx	JonasDC	4121d 03h	/mod_sim_exp/trunk
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4121d 03h	/mod_sim_exp/trunk
47	added documentation for the IP core.	JonasDC	4201d 03h	/mod_sim_exp/trunk
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4201d 03h	/mod_sim_exp/trunk
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4201d 03h	/mod_sim_exp/trunk
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4204d 21h	/mod_sim_exp/trunk
43	made the core parameters generics	JonasDC	4204d 21h	/mod_sim_exp/trunk
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4211d 05h	/mod_sim_exp/trunk