URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 55

Rev	Log message	Author	Age	Path
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4234d 05h	/mod_sim_exp/trunk/rtl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4234d 19h	/mod_sim_exp/trunk/rtl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4238d 04h	/mod_sim_exp/trunk/rtl
23	added descriptive comments	JonasDC	4238d 05h	/mod_sim_exp/trunk/rtl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4240d 23h	/mod_sim_exp/trunk/rtl
21	changed x_i signal to xi	JonasDC	4242d 06h	/mod_sim_exp/trunk/rtl
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4242d 06h	/mod_sim_exp/trunk/rtl
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4247d 01h	/mod_sim_exp/trunk/rtl
18	updated stages with comments and renamed some signals for consistency	JonasDC	4248d 01h	/mod_sim_exp/trunk/rtl
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4248d 06h	/mod_sim_exp/trunk/rtl