URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 63

Rev	Log message	Author	Age	Path
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4250d 03h	/mod_sim_exp/trunk/rtl
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4250d 06h	/mod_sim_exp/trunk/rtl
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4250d 09h	/mod_sim_exp/trunk/rtl
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4250d 10h	/mod_sim_exp/trunk/rtl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4250d 15h	/mod_sim_exp/trunk/rtl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4250d 16h	/mod_sim_exp/trunk/rtl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4251d 06h	/mod_sim_exp/trunk/rtl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4254d 15h	/mod_sim_exp/trunk/rtl
23	added descriptive comments	JonasDC	4254d 16h	/mod_sim_exp/trunk/rtl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4257d 10h	/mod_sim_exp/trunk/rtl