URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 87

Rev	Log message	Author	Age	Path
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4127d 15h	/mod_sim_exp/trunk/rtl
53	correctly inferred ram for altera dual port ram	JonasDC	4127d 22h	/mod_sim_exp/trunk/rtl
52	correct inferring of blockram, no additional resources.	JonasDC	4127d 22h	/mod_sim_exp/trunk/rtl
51	true dual port ram for xilinx	JonasDC	4127d 23h	/mod_sim_exp/trunk/rtl
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4127d 23h	/mod_sim_exp/trunk/rtl
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4207d 23h	/mod_sim_exp/trunk/rtl
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4211d 16h	/mod_sim_exp/trunk/rtl
43	made the core parameters generics	JonasDC	4211d 16h	/mod_sim_exp/trunk/rtl
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4218d 00h	/mod_sim_exp/trunk/rtl
41	removed deprecated files from version control	JonasDC	4218d 00h	/mod_sim_exp/trunk/rtl