URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 61

Rev	Log message	Author	Age	Path
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4217d 21h	/mod_sim_exp/trunk/rtl/vhdl
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4217d 22h	/mod_sim_exp/trunk/rtl/vhdl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4218d 03h	/mod_sim_exp/trunk/rtl/vhdl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4218d 03h	/mod_sim_exp/trunk/rtl/vhdl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4218d 17h	/mod_sim_exp/trunk/rtl/vhdl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4222d 02h	/mod_sim_exp/trunk/rtl/vhdl
23	added descriptive comments	JonasDC	4222d 03h	/mod_sim_exp/trunk/rtl/vhdl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4224d 21h	/mod_sim_exp/trunk/rtl/vhdl
21	changed x_i signal to xi	JonasDC	4226d 05h	/mod_sim_exp/trunk/rtl/vhdl
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4226d 05h	/mod_sim_exp/trunk/rtl/vhdl