URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 90

Rev	Log message	Author	Age	Path
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4123d 23h	/mod_sim_exp/trunk/rtl/vhdl
55	updated resource usage in comments	JonasDC	4127d 23h	/mod_sim_exp/trunk/rtl/vhdl
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4127d 23h	/mod_sim_exp/trunk/rtl/vhdl
53	correctly inferred ram for altera dual port ram	JonasDC	4128d 06h	/mod_sim_exp/trunk/rtl/vhdl
52	correct inferring of blockram, no additional resources.	JonasDC	4128d 06h	/mod_sim_exp/trunk/rtl/vhdl
51	true dual port ram for xilinx	JonasDC	4128d 07h	/mod_sim_exp/trunk/rtl/vhdl
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4128d 07h	/mod_sim_exp/trunk/rtl/vhdl
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4208d 07h	/mod_sim_exp/trunk/rtl/vhdl
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4212d 00h	/mod_sim_exp/trunk/rtl/vhdl
43	made the core parameters generics	JonasDC	4212d 00h	/mod_sim_exp/trunk/rtl/vhdl