URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core] - Rev 69

Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4230d 02h	/mod_sim_exp/trunk/rtl/vhdl/core
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4233d 11h	/mod_sim_exp/trunk/rtl/vhdl/core
23	added descriptive comments	JonasDC	4233d 12h	/mod_sim_exp/trunk/rtl/vhdl/core
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4236d 06h	/mod_sim_exp/trunk/rtl/vhdl/core
21	changed x_i signal to xi	JonasDC	4237d 13h	/mod_sim_exp/trunk/rtl/vhdl/core
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4237d 14h	/mod_sim_exp/trunk/rtl/vhdl/core
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4242d 09h	/mod_sim_exp/trunk/rtl/vhdl/core
18	updated stages with comments and renamed some signals for consistency	JonasDC	4243d 08h	/mod_sim_exp/trunk/rtl/vhdl/core
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4243d 13h	/mod_sim_exp/trunk/rtl/vhdl/core
16	package with modified generic parameter for register_n	JonasDC	4244d 02h	/mod_sim_exp/trunk/rtl/vhdl/core