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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core] - Rev 89

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36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4265d 20h /mod_sim_exp/trunk/rtl/vhdl/core
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4265d 23h /mod_sim_exp/trunk/rtl/vhdl/core
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4266d 02h /mod_sim_exp/trunk/rtl/vhdl/core
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4266d 03h /mod_sim_exp/trunk/rtl/vhdl/core
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4266d 08h /mod_sim_exp/trunk/rtl/vhdl/core
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4266d 09h /mod_sim_exp/trunk/rtl/vhdl/core
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4266d 22h /mod_sim_exp/trunk/rtl/vhdl/core
24 changed names of top-level module to mod_sim_exp_core JonasDC 4270d 07h /mod_sim_exp/trunk/rtl/vhdl/core
23 added descriptive comments JonasDC 4270d 09h /mod_sim_exp/trunk/rtl/vhdl/core
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4273d 02h /mod_sim_exp/trunk/rtl/vhdl/core

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