URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl] - Rev 60

Rev	Log message	Author	Age	Path
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4251d 07h	/mod_sim_exp/trunk/rtl/vhdl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4251d 12h	/mod_sim_exp/trunk/rtl/vhdl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4251d 13h	/mod_sim_exp/trunk/rtl/vhdl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4252d 03h	/mod_sim_exp/trunk/rtl/vhdl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4255d 12h	/mod_sim_exp/trunk/rtl/vhdl
23	added descriptive comments	JonasDC	4255d 13h	/mod_sim_exp/trunk/rtl/vhdl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4258d 06h	/mod_sim_exp/trunk/rtl/vhdl
21	changed x_i signal to xi	JonasDC	4259d 14h	/mod_sim_exp/trunk/rtl/vhdl
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4259d 14h	/mod_sim_exp/trunk/rtl/vhdl
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4264d 09h	/mod_sim_exp/trunk/rtl/vhdl