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[/] [mod_sim_exp/] [trunk/] [rtl] - Rev 55

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30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4238d 02h /mod_sim_exp/trunk/rtl
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4238d 16h /mod_sim_exp/trunk/rtl
24 changed names of top-level module to mod_sim_exp_core JonasDC 4242d 01h /mod_sim_exp/trunk/rtl
23 added descriptive comments JonasDC 4242d 02h /mod_sim_exp/trunk/rtl
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4244d 20h /mod_sim_exp/trunk/rtl
21 changed x_i signal to xi JonasDC 4246d 03h /mod_sim_exp/trunk/rtl
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4246d 04h /mod_sim_exp/trunk/rtl
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4250d 23h /mod_sim_exp/trunk/rtl
18 updated stages with comments and renamed some signals for consistency JonasDC 4251d 22h /mod_sim_exp/trunk/rtl
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4252d 03h /mod_sim_exp/trunk/rtl

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