URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk] - Rev 89

Rev	Log message	Author	Age	Path
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4119d 10h	/mod_sim_exp/trunk
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4127d 02h	/mod_sim_exp/trunk
64	added synthesis reports of xilinx and altera	JonasDC	4127d 08h	/mod_sim_exp/trunk
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4127d 08h	/mod_sim_exp/trunk
62	not used anymore	JonasDC	4127d 10h	/mod_sim_exp/trunk
61	updated comments, added optional altera constraint	JonasDC	4127d 10h	/mod_sim_exp/trunk
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4130d 01h	/mod_sim_exp/trunk
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4130d 01h	/mod_sim_exp/trunk
55	updated resource usage in comments	JonasDC	4134d 01h	/mod_sim_exp/trunk
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4134d 01h	/mod_sim_exp/trunk