URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 75

Rev	Log message	Author	Age	Path
55	updated resource usage in comments	JonasDC	4127d 10h	/mod_sim_exp
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4127d 10h	/mod_sim_exp
53	correctly inferred ram for altera dual port ram	JonasDC	4127d 16h	/mod_sim_exp
52	correct inferring of blockram, no additional resources.	JonasDC	4127d 17h	/mod_sim_exp
51	true dual port ram for xilinx	JonasDC	4127d 17h	/mod_sim_exp
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4127d 18h	/mod_sim_exp
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4139d 13h	/mod_sim_exp
48	Tag of the starting version of the project	JonasDC	4139d 13h	/mod_sim_exp
47	added documentation for the IP core.	JonasDC	4207d 17h	/mod_sim_exp
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4207d 17h	/mod_sim_exp