URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp] - Rev 86

Rev	Log message	Author	Age	Path
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4099d 20h	/mod_sim_exp
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4107d 12h	/mod_sim_exp
64	added synthesis reports of xilinx and altera	JonasDC	4107d 18h	/mod_sim_exp
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4107d 18h	/mod_sim_exp
62	not used anymore	JonasDC	4107d 21h	/mod_sim_exp
61	updated comments, added optional altera constraint	JonasDC	4107d 21h	/mod_sim_exp
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4110d 11h	/mod_sim_exp
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4110d 11h	/mod_sim_exp
58	made fifo full a warning	JonasDC	4113d 11h	/mod_sim_exp
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4113d 11h	/mod_sim_exp