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[/] [open8_urisc/] - Rev 226

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Rev Log message Author Age Path
206 Merged interrupt logic with other clocked process. jshamlet 1659d 02h /open8_urisc
205 More code and comment cleanup for the new SDLC engine jshamlet 1659d 02h /open8_urisc
204 Fixed more incorrect comments jshamlet 1659d 03h /open8_urisc
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1659d 09h /open8_urisc
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.
jshamlet 1659d 10h /open8_urisc
201 Fixed comments regarding RX Checksum location jshamlet 1661d 07h /open8_urisc
200 Renamed dual-port buffer to match other entities. jshamlet 1661d 07h /open8_urisc
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1661d 07h /open8_urisc
198 Removed debugging memory jshamlet 1661d 16h /open8_urisc
197 Fixed incorrect comments jshamlet 1661d 16h /open8_urisc

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