URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 303

Rev	Log message	Author	Age	Path
283	Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop.	jshamlet	1308d 04h	/open8_urisc
282	Modified the SDLC core transmit states to have consistent naming.	jshamlet	1308d 04h	/open8_urisc
281	Added pre-initialization to the dual-port RAM signals.	jshamlet	1308d 07h	/open8_urisc
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1308d 08h	/open8_urisc
279	More comment cleanup	jshamlet	1309d 05h	/open8_urisc
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1309d 23h	/open8_urisc
277	Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag.	jshamlet	1310d 05h	/open8_urisc
276	More comment fixes	jshamlet	1345d 01h	/open8_urisc
275	Fixed a minor comment error.	jshamlet	1346d 20h	/open8_urisc
274	Updated comments with more corrections	jshamlet	1347d 02h	/open8_urisc