URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 217

Rev	Log message	Author	Age	Path
154	Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed.	jshamlet	4725d 06h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
153	Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded, Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.	jshamlet	4752d 01h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
151	Fixed STO instruction and interrupt logic to avoid address bus corruption issues.	jshamlet	4762d 04h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
10	corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values	khays	4903d 13h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
8	Need to learn SVN...	jshamlet	5232d 01h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
7	Initial Upload	jshamlet	5232d 01h	/open8_urisc/trunk/open8_urisc/VHDL/o8_cpu.vhd