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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 255

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183 Renamed core to o8_cpu to match new naming scheme jshamlet 1582d 03h /open8_urisc/trunk/VHDL/o8_cpu.vhd
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1582d 03h /open8_urisc/trunk/VHDL/Open8.vhd
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1583d 00h /open8_urisc/trunk/VHDL/Open8.vhd
172 General code cleanup jshamlet 3107d 01h /open8_urisc/trunk/VHDL/Open8.vhd
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3162d 02h /open8_urisc/trunk/VHDL/Open8.vhd
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3940d 22h /open8_urisc/trunk/VHDL/Open8.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3948d 21h /open8_urisc/trunk/VHDL/Open8.vhd
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4584d 16h /open8_urisc/trunk/VHDL/Open8.vhd
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4675d 09h /open8_urisc/trunk/VHDL/Open8.vhd
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4732d 00h /open8_urisc/trunk/VHDL/Open8.vhd

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