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[/] [open8_urisc/] [trunk/] [VHDL] - Rev 290

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268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1394d 17h /open8_urisc/trunk/VHDL
267 Corrected the file description to indicate this is an example package. jshamlet 1394d 17h /open8_urisc/trunk/VHDL
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1394d 17h /open8_urisc/trunk/VHDL
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1487d 02h /open8_urisc/trunk/VHDL
264 Updated comments jshamlet 1496d 23h /open8_urisc/trunk/VHDL
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.		 jshamlet 1496d 23h /open8_urisc/trunk/VHDL
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1506d 03h /open8_urisc/trunk/VHDL
261 Increased delay timer to 7 bits for button press detection. jshamlet 1513d 03h /open8_urisc/trunk/VHDL
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1526d 02h /open8_urisc/trunk/VHDL
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.		 jshamlet 1526d 03h /open8_urisc/trunk/VHDL

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