OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk] - Rev 38

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 The device can now program and configure itself, allowing bootstrap possibilities.
`
dgisselq 2910d 16h /openarty/trunk
17 Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works.
dgisselq 2912d 15h /openarty/trunk
16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.
dgisselq 2912d 15h /openarty/trunk
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.
dgisselq 2912d 16h /openarty/trunk
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.
dgisselq 2912d 16h /openarty/trunk
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).
dgisselq 2912d 16h /openarty/trunk
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.
dgisselq 2913d 19h /openarty/trunk
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.
dgisselq 2913d 19h /openarty/trunk
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.
dgisselq 2913d 19h /openarty/trunk
9 Adding copywrite statement (oops). dgisselq 2913d 19h /openarty/trunk

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.