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16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.		 dgisselq 2925d 15h /openarty
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.		 dgisselq 2925d 16h /openarty
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.		 dgisselq 2925d 16h /openarty
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).		 dgisselq 2925d 16h /openarty
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.		 dgisselq 2926d 19h /openarty
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2926d 19h /openarty
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2926d 19h /openarty
9 Adding copywrite statement (oops). dgisselq 2926d 19h /openarty
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2926d 19h /openarty
7 This implements the coordination of a massive build/test suite--just not the
actual configuration file itself.		 dgisselq 2926d 19h /openarty

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