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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog] - Rev 205

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111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4766d 16h /openmsp430/trunk/core/rtl/verilog
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4822d 15h /openmsp430/trunk/core/rtl/verilog
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4837d 16h /openmsp430/trunk/core/rtl/verilog
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4842d 22h /openmsp430/trunk/core/rtl/verilog
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4843d 15h /openmsp430/trunk/core/rtl/verilog
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4843d 17h /openmsp430/trunk/core/rtl/verilog
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4855d 17h /openmsp430/trunk/core/rtl/verilog
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4878d 14h /openmsp430/trunk/core/rtl/verilog
85 Diverse RTL cosmetic updates. olivier.girard 4878d 16h /openmsp430/trunk/core/rtl/verilog
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4883d 17h /openmsp430/trunk/core/rtl/verilog

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