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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim] - Rev 154

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94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4874d 09h /openmsp430/trunk/core/sim/rtl_sim
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4878d 10h /openmsp430/trunk/core/sim/rtl_sim
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4901d 07h /openmsp430/trunk/core/sim/rtl_sim
85 Diverse RTL cosmetic updates. olivier.girard 4901d 09h /openmsp430/trunk/core/sim/rtl_sim
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4955d 16h /openmsp430/trunk/core/sim/rtl_sim
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4967d 10h /openmsp430/trunk/core/sim/rtl_sim
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4972d 09h /openmsp430/trunk/core/sim/rtl_sim
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5054d 10h /openmsp430/trunk/core/sim/rtl_sim
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5079d 10h /openmsp430/trunk/core/sim/rtl_sim
72 Expand configurability options of the program and data memory sizes. olivier.girard 5081d 11h /openmsp430/trunk/core/sim/rtl_sim

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