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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim] - Rev 178

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Rev	Log message	Author	Age	Path
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4869d 20h	/openmsp430/trunk/core/sim/rtl_sim
95	Update some test patterns for the additional simulator supports.	olivier.girard	4873d 20h	/openmsp430/trunk/core/sim/rtl_sim
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4873d 20h	/openmsp430/trunk/core/sim/rtl_sim
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4877d 21h	/openmsp430/trunk/core/sim/rtl_sim
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4900d 17h	/openmsp430/trunk/core/sim/rtl_sim
85	Diverse RTL cosmetic updates.	olivier.girard	4900d 19h	/openmsp430/trunk/core/sim/rtl_sim
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4955d 03h	/openmsp430/trunk/core/sim/rtl_sim
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4966d 21h	/openmsp430/trunk/core/sim/rtl_sim
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4971d 19h	/openmsp430/trunk/core/sim/rtl_sim
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5053d 20h	/openmsp430/trunk/core/sim/rtl_sim

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