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[/] [openmsp430/] [trunk/] [fpga/] - Rev 162

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105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4858d 16h /openmsp430/trunk/fpga
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4862d 17h /openmsp430/trunk/fpga
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4867d 16h /openmsp430/trunk/fpga
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4868d 16h /openmsp430/trunk/fpga
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4869d 16h /openmsp430/trunk/fpga
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4872d 16h /openmsp430/trunk/fpga
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4876d 17h /openmsp430/trunk/fpga
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4899d 14h /openmsp430/trunk/fpga
85 Diverse RTL cosmetic updates. olivier.girard 4899d 16h /openmsp430/trunk/fpga
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4904d 17h /openmsp430/trunk/fpga

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