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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit] - Rev 200

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105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4871d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4875d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4881d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4885d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4889d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4912d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
85 Diverse RTL cosmetic updates. olivier.girard 4912d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4917d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4963d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4963d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit

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