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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit] - Rev 212

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112 Modified comment. olivier.girard 4779d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4780d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4836d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4836d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4851d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4855d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4861d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4865d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4869d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4892d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit

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