OpenCores

URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 182

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5296d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
61	Update openMSP430 rtl.	olivier.girard	5328d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5330d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5335d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
37		olivier.girard	5364d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
36	Remove old core version.	olivier.girard	5364d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5375d 03h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5375d 03h	/openmsp430/trunk/fpga/diligent_s3board/rtl
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5485d 23h	/openmsp430/trunk/fpga/diligent_s3board/rtl
16	Updated header with SVN info	olivier.girard	5511d 19h	/openmsp430/trunk/fpga/diligent_s3board/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.