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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl] - Rev 205

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105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4876d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4880d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4894d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4917d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
85 Diverse RTL cosmetic updates. olivier.girard 4917d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4922d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4983d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5070d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
72 Expand configurability options of the program and data memory sizes. olivier.girard 5097d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5244d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl

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