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[/] [openmsp430/] [trunk/] [fpga] - Rev 156

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Rev	Log message	Author	Age	Path
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4887d 20h	/openmsp430/trunk/fpga
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4888d 20h	/openmsp430/trunk/fpga
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4891d 20h	/openmsp430/trunk/fpga
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4895d 21h	/openmsp430/trunk/fpga
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4918d 18h	/openmsp430/trunk/fpga
85	Diverse RTL cosmetic updates.	olivier.girard	4918d 19h	/openmsp430/trunk/fpga
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4923d 21h	/openmsp430/trunk/fpga
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	4969d 21h	/openmsp430/trunk/fpga
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4969d 21h	/openmsp430/trunk/fpga
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4972d 19h	/openmsp430/trunk/fpga

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