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[/] [openmsp430/] [trunk/] [fpga] - Rev 188

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143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4442d 04h /openmsp430/trunk/fpga
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4458d 13h /openmsp430/trunk/fpga
136 Update all FPGA projects with the latest core version. olivier.girard 4490d 03h /openmsp430/trunk/fpga
132 Update FPGA examples with the POP.B bug fix olivier.girard 4503d 03h /openmsp430/trunk/fpga
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4587d 03h /openmsp430/trunk/fpga
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4731d 04h /openmsp430/trunk/fpga
112 Modified comment. olivier.girard 4796d 03h /openmsp430/trunk/fpga
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4797d 03h /openmsp430/trunk/fpga
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4851d 12h /openmsp430/trunk/fpga
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4853d 01h /openmsp430/trunk/fpga

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