URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430] - Rev 120

Rev	Log message	Author	Age	Path
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4911d 07h	/openmsp430
99	Small fix for CVER simulator support.	olivier.girard	4912d 08h	/openmsp430
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4912d 08h	/openmsp430
97	Update Tools' Windows executables with EraseROM command fix.	olivier.girard	4913d 08h	/openmsp430
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4913d 08h	/openmsp430
95	Update some test patterns for the additional simulator supports.	olivier.girard	4916d 08h	/openmsp430
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4916d 08h	/openmsp430
93	Update Tools' Windows executables.	olivier.girard	4920d 07h	/openmsp430
92	Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size. Thanks to "dir" for reporting the bug :-)	olivier.girard	4920d 08h	/openmsp430
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4920d 08h	/openmsp430