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[/] [openmsp430] - Rev 135

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115 Add linker script example. olivier.girard 4793d 13h /openmsp430
114 Improved the VerifyCPU_ID procedure. olivier.girard 4796d 12h /openmsp430
113 Created ChangeLog files... olivier.girard 4797d 12h /openmsp430
112 Modified comment. olivier.girard 4801d 12h /openmsp430
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4802d 12h /openmsp430
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4803d 12h /openmsp430
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4856d 21h /openmsp430
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4858d 10h /openmsp430
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4858d 10h /openmsp430
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4858d 11h /openmsp430

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