URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430] - Rev 136

Rev	Log message	Author	Age	Path
116	Update documentation to reflect the latest core updates.	olivier.girard	4813d 08h	/openmsp430
115	Add linker script example.	olivier.girard	4822d 07h	/openmsp430
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4825d 06h	/openmsp430
113	Created ChangeLog files...	olivier.girard	4826d 07h	/openmsp430
112	Modified comment.	olivier.girard	4830d 06h	/openmsp430
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4831d 06h	/openmsp430
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4832d 06h	/openmsp430
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4885d 15h	/openmsp430
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4887d 04h	/openmsp430
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4887d 04h	/openmsp430