URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 73

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5362d 01h	/openrisc
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5362d 21h	/openrisc
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5376d 23h	/openrisc
50	Adding or32_funcs.S	julius	5377d 03h	/openrisc
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5395d 17h	/openrisc
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5395d 20h	/openrisc
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5405d 03h	/openrisc
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5411d 04h	/openrisc
45	Orpsoc eth test fix and script error message update	julius	5418d 04h	/openrisc
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5447d 03h	/openrisc