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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [doc] - Rev 347

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Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5178d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5179d 20h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5181d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
104	Candidate release 0.4.0rc4	jeremybennett	5185d 03h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5193d 20h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
100	Single precision FPU stuff for or1ksim	julius	5193d 23h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
99	Bug in test evaluation for library fixed.	jeremybennett	5198d 21h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5199d 22h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5214d 04h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5215d 05h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc

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